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Full job description
Duration of the project: 3 months to begin with; extension later

Desired start date: 17th February 2025

Experience: 8+ Years

Requirements :

B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN’s.
Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, bandgap references, oscillators/clocking circuits, Phase Interpolators, SerDes etc. and related digital control and signal processing.
Demonstrated experience of verification plan development, UVM verification environment development/debug and verification of complex mixed signal products at block, Subsystem & chip-top levels.
Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision.
Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators.
Experience and debug with digital simulators such as Cadence Xcelium/DMSO/Synopsys VCS.
Experience in developing self-checking testcases, functional/code coverage & formal verification.
Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager.
Experience in closing the verification of analog designs using industry standard metrics is a must.
Quick to adopt new technologies with good problem-solving skills.
Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc.).
Self-motivated and enthusiastic.
Job Type: Contractual / Temporary
Contract length: 3 months

Pay: ₹100,000.00 – ₹300,000.00 per month

Benefits:

Health insurance
Schedule:

Day shift
Monday to Friday
Application Question(s):

Have you experienced in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN’s.
Education:

Bachelor’s (Preferred)
Experience:

total work: 8 years (Required)
full chip verification (AMS and DMS DV): 8 years (Required)
Work Location: In person